The past few years have seen a dramatic increase in the speed of data transmission between various components of a computer system or between multiple computer systems connected together in a network. Indeed, since general acceptance of personal computer systems in the 1960's, data transmission speeds have grown with an almost power law dependence; about 1 MHz in the '60's, 10 MHz in the '70's, 100 MHz in the '80's, and 1 GHz speeds being routinely achieved in the '90's.
Optical fibre is a particular enabling technology for modern day 1 GHz data transmission speeds and, in the computer industry, has given rise to a data transfer protocol and interface system termed Fibre-Channel. Fibre-Channel technology involves coupling various computer systems together with optical fibre or a fibre channel-type electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by relatively great distances. However, because of the physical characteristics of fibre channel-type cable, present day systems are only capable of serial-fashion data transmission (at least when only a single optical fibre or electrical cable is used to interconnect various computer systems). However, computer systems are constructed to almost universally handle data in parallel fashion on byte-multiple signal busses (8-bit, 16-bit or 32-bit busses), making it incumbent on any data transmission system to provide some means for converting a 1 GHz serial data stream into a byte or byte-multiple parallel data stream. Conversely, since the fibre channel protocol is 2-way, computer systems that typically operate with parallel data structures, must have some means for serializing a byte or byte-multiple data stream into a 1 GHz data signal suitable for transmission down an optical fibre or electrically conductive (copper) cable.
Parallel data being serialized for high speed transmission, is typically synchronous, in that the sequence of 1's and 0's making up the resulting serial data stream occurs with reference to a uniform or single-frequency serializer clock signal. Encoding and transmitting the clock signal, together with the data, would take up inordinate amounts of valuable signal bandwidth and reduce the overall data transmission speed of a fibre channel system. Even though some small degree of self-clocking is inherent in the serial data stream, some method of evaluating the data stream must be used in order that a transceiver or serial-to-parallel data recovery system may determine how to appropriately frame the binary data stream into bytes.
In many applications, this function is performed by various types of data synchronizers, which generate or regenerate a synchronous timing reference signal from a serial data stream and provides the timing reference to a serial-to-parallel converter, such as a sequential latch. In effect, a data synchronizer generates a synchronous stream of successive timing references, each timing reference representing a bit cell with which a data bit is associated. For example, 10 consecutive timing references might represent an 8-bit data word followed by 2 bits of error correction code which might then be latched out onto a 10-bit parallel data bus by a, for example, 10-bit counter. The data synchronizer, accordingly, is an essential component in modern day gigahertz serial to parallel data converters.
However, the frequency of clock signals synthesized by such circuitry is subject to a number of variations introduced by the electronic components of such systems. Typically, the electronic components in the data path introduce elements of phase and frequency noise which are random in nature and, more particularly, have dramatically varying bandwidth characteristics depending on the geometric and electronic variations in modern semiconductor manufacturing process parameters. A synchronizer, such as a 1.06 GHz to 106 MHz Transceiver, must take these variations into account when attempting to deal with a 1.06 GHz serial data stream. Implementations of such a synchronizer or transceiver, typically include at least phase-locked loop (PLL), normally comprising a phase or phase and frequency detector, a charge pump, an analog filter, and means for generating asynchronous clock signal, such as a voltage control oscillator (VCO). When receiving data, during what is conventionally termed frequency or velocity lock, the oscillation frequency of the VCO is determined by, and locked to the frequency of an external clock provided for such purpose, just prior to receiving the serial data stream. Once frequency or velocity lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock. Subsequent correction control to the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of an incoming data signal. The VCO is phase-locked to the incoming serial data stream by comparing the phase of the rising edge of the VCO clock signal to the phase of the rising edge of a data One (1) bit, in a phase detector. A phase or time difference detected between the two rising edges causes the phase detector to issue a signal to the charge pump which, in turn, generates a control voltage through an analog filter, directing the VCO to either speed up or slow down in response to frequency variation in the data stream.
An analog low pass filter is typically provided between the charge pump and the VCO to reject corrections resulting from random high-frequency variations of individual data bits, and allow ideally only corrections resulting from consistent frequency shifts of the data stream. The VCO is therefore locked to the mean phase of the data stream, rather than to the phase of a particular data bit. Once phase-locked, the synchronous VCO signal provides for a recovered clock signal whose rate (frequency) is equal to the data bit rate or an integral multiple thereof.
A typical prior art phase-lock loop system is illustrated in FIG. 1, and is connected to receive an incoming serial data stream from, for example, an optical fibre cable 10. The phase-lock loop suitably comprises a type-IV phase detector 11 (also referred to as a Charlie Hogge-type phase detector), coupled to a charge pump 12, operatively connected in turn to an analog filter 13 and a voltage controlled oscillator or VCO 14.
Serial data is received over the, for example, optical cable 10 at a data input of the phase detector 11, in which the occurrence of its rising edge (its phase) is compared in time to the occurrence of the rising edge (the phase) of an output signal of the VCO 14. Conventionally, the phase detector incorporates logic circuitry (in effect a logical NOR function) which precludes an output signal from being issued during phase comparisons unless two rising edges are present during a comparison cycle. This feature prevents the phase-lock loop from becoming unstable by trying to perform a phase comparison between a VCO rising edge and a data ZERO bit (necessarily without a rising edge). It will be understood that the phase comparison result in such a situation would indicate either an infinite phase lead or an infinite phase lag, thus causing the VCO frequency to significantly shift.
Certain prior art systems have attempted to overcome this potential instability by delaying the data stream in time by a delay line and directing the resulting delayed data to the data input of the phase detector 11. Data signals, prior to being directed through the delay line, are also applied to an enable input of the phase comparator as well as to the input of the delay line. The enable input of the phase detector is configured such that it receives a data ONE pulse just prior to the same data ONE pulse appearing at the data input of the phase detector. The phase detector is further configured so that phase comparisons are precluded, or phase comparisons do not result in an output signal, unless the phase comparator has been enabled by a data ONE bit. In operation, if the data stream comprises a series of data ZEROS, no enable signal will be directed to the phase detector and no phase comparisons will be performed. At each occurrence of a data ONE bit, the raw data ONE signal will enable the phase detector just prior to the delayed data ONE signal reaching the data input. A phase comparison between the leading edge of the data ONE signal and the leading edge of the VCO signal is now allowed to take place.
While this method is relatively successful for PLL's operating at relatively low frequencies (approximately 10 MHz), it will be understood that such a system does not realize adequate performance for data rates in the 1 GHz range.
In contrast to the PLL systems described above, a Charlie Hogge-type (or type-IV) phase detector is in continuous operation, and issues continuous pump-up and pump-down commands to a charge pump regardless of the logical state of an incoming data bit. It might be said that a Charlie Hogge-type phase detector operates in a "quasi flywheel" mode when the incoming data stream comprises a sequence of data ZEROS and modulates the pump-up or pump-down signal in response to a phase comparison only for the occurrence of a logical ONE at the data input.
The output of the phase detector 11 comprises a pump-up (or UP) 16 and a pump-down (or DN) 18 signal which, in turn, direct the charge pump 12 to either source or sink current to or from the analog filter 13 which develops a voltage control signal for adjusting the speed of the VCO 14.
According to convention, the phase detector 11 issues UP 16 if the data stream leads the VCO signal, and issues DN 18 if the serial data stream phase lags the signal stream from the VCO 14. UP 16 and DN 18 are directed to the charge pump 12 which sources or sinks a particular amount of current (noted herein I.sub.CP) to or from, respectively, a capacitor comprising the filter 13. A voltage is developed as the charge pump current I.sub.CP is sourced or sunk to or from the capacitor. Thus voltage is used to control the VCO. The sign of the VCO control voltage variation depends on whether the phase of the data stream leads or lags the phase of the VCO output, and its magnitude is a function of the extent of the phase lead or phase lag. Thus, the operating frequency of the VCO 14 is increased or decreased, as appropriate, to reduce the phase lead or phase lag of the inputs to the phase detector 11. The phase-locked loop thus ensures that the VCO output, which may be used as a timing reference, is locked in phase with the incoming serial data stream.
A particular shortcoming of prior art phase lock loop systems is that the charge pump is required to source and sink current which precisely represents the magnitude and polarity of a phase difference between an incoming data ONE signal and the VCO. In addition, for a type-IV phase detector operating in a quasi flywheel mode during the occurrence of data ZEROS, the charge pump is required to source and sink current in such a manner that the output current, averaged over a correction cycle, equals zero. In other words, the charge pump should ideally only cause corrections to be made to the operating characteristics of the VCO which result from consistent frequency shifts of the data stream, such that the VCO is locked to the mean phase of the incoming data stream rather than to the phase of any particular data bit.
Maintaining perfect phase-lock of VCO to data, however, is particularly difficult for conventional prior art-type phase-lock loop circuits operating in the GHz range, because of the internal construction of conventional prior art-type charge pump circuits. In addition, the source and sink current waveforms, of such conventional charge pump circuits, exhibit significant amounts of ringing and "glitch errors" which cause the source and sink current waveforms to be non-symmetrical. This non-symmetry necessarily results in a residual charge being left on the filter capacitor at the end of a correction cycle and further causes a non-zero increment to the control voltage V.sub.C to the VCO.
The terms "ringing" and "glitch errors" refer to fluctuations in the source and/or sink current waveforms and represent quantifiable departures from a smooth waveform characteristic. As will be described in greater detail below, these fluctuations are caused by a variety of factors, the majority of which are functions of the physical and electrical properties of semiconductor integrated circuit transistors and integrated circuit charge pumps manufactured therefrom.
To better understand the effects of "ringing" and "glitch errors" on the stability of a phase-lock loop, it will be helpful to review the operation of a PLL, such as illustrated in FIG. 1, having recourse to the waveform diagrams of FIGS. 2a-2g. In the waveform diagrams of FIGS. 2a-2g, 2a represents a VCO signal train as would be developed by a VCO 14 and provided to the VCO input of a type-IV phase detector 11. FIG. 2b represents the occurrence of a data ONE followed by a sequence of data zeros as would be provided at the data input of the phase detector 11. It should be noted that the periodicity of the VCO signal train defines a sequence of intervals, with each interval representing a phase correction cycle. For purposes of illustration only, the correction intervals are depicted between sequential VCO signal rising edges. FIGS. 2c and 2d illustrate a pump-up and pump-down pulse, respectively, provided by the phase detector during correction cycles in which no data ONE bit appears, in accordance with the conventionally understood operation of a type-IV phase detector. When a PLL is operating in quasi flywheel mode, the phase detector conventionally issues a pump-up signal having a characteristic pulse width, T, immediately followed by a pump-down signal having the same pulse width, T. Although only a single pump-up and pump-down signal is depicted in FIGS. 2c and 2d, it will be understood that type-IV phase detectors often operate by issuing continuous pump-up and pump-down signals and that such signals are not necessarily 180 degrees out of phase with one another. Indeed, pump-up and pump-down may be issued simultaneously, 90 degrees out of phase, or with any other consistent phase relationship defined by the circuit designer.
The pump-up and pump-down pulses depicted in FIGS. 2c and 2d give rise to positive and negative charge pump currents (+I.sub.CP and -I.sub.CP) as depicted in FIGS. 2e and 2f. A positive I.sub.CP represents current sourced to a capacitor in the filter section 13 of the PLL in response to a pump-up signal issued by the phase detector 11, while a negative I.sub.CP represents current sunk from the filter capacitor in response to a pump-down signal from the detector 11. Each of the currents, +I.sub.CP and -I.sub.CP have a specific magnitude (I.sub.CP) and a characteristic pulse length which is, ideally, equal to the pulse length of the pump-up and pump-down pulses, T.
As depicted in FIG. 2g, a positive charge pump current (+I.sub.CP) causes a charge to accumulate on the filter capacitor which results in a linear voltage characteristic (in the positive direction) being applied to the V.sub.C output of the filter 13. As the charge pump current changes from positive to negative, the negative current (-I.sub.CP) removes charge from the filter capacitor, causing the V.sub.C voltage to decline in a linear fashion to its originally held value. In order not to perturb the PLL system, the output voltage of the filter section 13 (V.sub.C) must return to its nominal value if the PLL is operating "quasi flywheel". It is only when a phase comparison is taking place and there is some phase lead or phase lag detected by the phase detector 11, that the final V.sub.C value will be different from the initial V.sub.C value.
In order for V.sub.C to retain its nominal value following a quasi flywheel correction cycle, it is necessary that the amount of charge introduced to the filter capacitor exactly equal to the amount of charge removed from the filter capacitor during the cycle. For this condition to hold, it is therefore necessary for the amount of current (+I.sub.CP) sourced to the capacitor to be identically equal to the amount of current (-I.sub.CP) sunk from the capacitor. Accordingly, the current waveforms of FIGS. 2e and 2f must be precisely symmetrical such that the average of the two currents sums to exactly zero.
The effects of "ringing" and "glitch errors" on the symmetry of source and sink current waveforms are illustrated in the waveform diagrams of FIG. 3. As can be seen in FIG. 3, as the charge pump sources current in response to a pump-up signal, the characteristic rise time of the +I.sub.CP waveform is neither smooth, uniform nor sharply vertical. Rather, the current response characteristic exhibits a slope in the attack portion that is a function, in turn, of the transistor turn-on characteristics of the charge pump output section.
As the current waveform reaches its nominal (I.sub.CP) saturation value, the waveform characteristic does not immediately roll-over and flatten out its nominal value, but instead "rings" or oscillates in a nonuniform fashion about the nominal current output value. This ringing implies that the absolute value of the current being sourced by the charge pump exceeds, at times, its nominal value while at other times fall significantly below its nominal value before settling. Moreover, as the charge pump transitions from sourcing current to sinking current, the turnoff characteristics of the output transistors cause the output current characteristic to exhibit a decay response rather than a sharply vertical instantaneous shut-off. This decay response also exhibits oscillation or ringing in at the end of conduction, with the output current at times exceeding zero and at other times going negative before settling.
In like fashion, as current is being sunk by the charge pump, the current characteristic exhibits a sloped turn-on, substantial ringing or oscillation, a characteristic delay shape at turn-off ending in substantial ringing as the charge pump output goes to zero.
As can also be seen from FIG. 3, the turn-on and turn-off portions (attack and decay) of the source and sink waveforms are not symmetrical. In addition, notwithstanding the non-uniform frequency and non-uniform decay characteristics of the glitch oscillations, the shape and excursion magnitudes (i.e., the glitch envelope) are different for sourced current as opposed to sunk current. As will be described further, the inherent internal construction of prior art charge pumps precludes sourced current pulses from exactly symmetrically mirroring sink current pulses, such that the amount of charge deposited on a filter capacitor is not equal to the amount of charge removed from the filter capacitor. The control voltage V.sub.C will necessarily be perturbed and take on a final value which is incrementally larger or smaller than its initial value (larger in the illustration of FIG. 3), depending on whether the residual charge on the filter capacitor is positive or negative. This lack of symmetry has significant implications for high speed low-error-rate phase-locked loop systems.
In practical terms, lack of perfect symmetry between sourced and sunk current selectively adds a small component (a glitch error component) to the Control Voltage V.sub.C provided to the VCO. This glitch error component selectively shifts the frequency of the VCO relative to the nominal center frequency of the VCO desired to be maintained during quasi fly-wheel operation. Any offset from the center frequency will cause the phase detector's data capture window to shift and allow a portion of a data pulse position distribution to fall outside the detection window, increasing the error rate.
As mentioned above, the lack of symmetry between a charge pump's sourced current and sunk current is inherent in the transistor elements used to construct prior art charge pumps, as illustrated in FIG. 4.
FIG. 4 illustrates, in simplified semi-schematic block diagrammatic form, a typical prior art-type 3-state charge pump, connected to receive pump-up and pump-down signals from a phase detector 19. The charge pump is implemented as two switched current sources 20 and 22 driving a capacitor 24, which, in turn, defines an output voltage (V.sub.OUT OR V.sub.C). The charge pump switches comprise an upper and lower switch bank, the upper switch bank comprising a pair of P-channel transistors 26 and 28 coupled at their source terminals to the upper current source 20 and whose drains are connected to the drains of a corresponding pair of N-channel transistors 30 and 32 which comprise the lower switch stack. The lower switch stack transistors have their source terminals connected in common and to the second current source 22. For purposes of explanation, it will be assumed that the upper current source 20 is implemented with PFETs and the lower current source 22 is implemented with NFETs according to well understood convention.
In operation, a pump-up pulse of width T would cause a positive output current +I.sub.CP to deposit a charge equal to (I.sub.CP T) on the capacitor 24. Likewise, a pump-down pulse of width T would cause a negative current -I.sub.CP to remove a charge equal to (I.sub.CP T) from the capacitor 24. Thus, in the case of a phase difference, either a positive charge would steadily accumulate on the capacitor, yielding an infinite DC gain for the phase detector, or charge would be steadily removed from the capacitor on every phase comparison, driving DC gain toward negative infinity. In the third state, i.e., lock, the steady state gain is assumed to be zero.
An important implication to this type of charge pump design is that offsets and mismatches between the pump-up and pump-down switch transistors would result in currents being either sourced to or sunk from the capacitor even though the phase detector experiences zero static phase difference at the inputs. Mismatch error is introduced into the behavior of prior art-type charge pumps by implementing the current source switches from different transistor types, i.e., N-channel and P-channel transistors. When these switches turn-off, charge injection and feed-through mismatch, inherent in the different physical properties of P-channel and N-channel transistors, results in an error step at the output which may change the VCO frequency until the next phase comparison cycle. Moreover, when the switches are turned-off, the upper and lower pump currents, I.sub.CP, generated by the respective current sources 20 and 22, pull their respective source nodes to VDD and ground causing charge-sharing between the capacitor 24 and the internal parasitic capacitances of the various transistors, when the switches are again turned-on. Since the internal parasitic capacitances of N-channel and P-channel transistors are significantly different, the output is significantly disturbed at turn-on. In addition to disturbing the output at turn-on, the well understood parametric differences between N-channel and P-channel transistors necessarily results in the quantifyable glitches introduced at the output for pump-up and pump-down to be different and, hence, the average output current to be non-zero.
Accordingly, prior art-type charge pump circuits do not provide an exact and constant symmetrical relationship between source and sink currents during phase lock, thus introducing variation in the VCO output. This variability becomes proportionately more significant as the VCO frequency increases. Accordingly, for high-speed phase-locked loops, operating in the 1 GHz range, there is a demonstrated need for a high precision charge pump which is designed and constructed such that glitch errors and oscillations are symmetrical for both the source and sink phases of a type-IV phase detection cycle, such that the average current, integrated across a cycle, more closely approximates zero.